The present invention relates generally to semiconductor devices, and more particularly, to improvements in source-drain structure of the MIS type semiconductor devices.
2. Description of the Background Art
As structure of semiconductor devices gets more and more miniaturized, the gate length of an MOS (Metal Oxide Semiconductor) transistor has been required to be 1.mu.m or less. In such a miniaturized structure, diffusion depth of source/drain regions has been made shallower, or a gate insulating film has been thinned according to the reduction of the gate length so as to suppress any degradation in characteristics which might be seen in a miniaturized transistor. As a result, an enhanced driving ability thereof has been obtained. Supply voltage for driving such MOS transistors, however, has not been reduced, but kept at a definite value, for example, at 5V, as in conventional cases. Therefore, electrical fields in devices were increased due to the miniaturized device structure such as in a transistor, which has brought about a problem of degradation in characteristics caused by hot carriers. Particularly, underneath gate electrodes in the vicinity of drain regions there was concentrated an internal electrical field so that the hot carriers are injected in a gate oxide film, generating trap state or interface state, which has led to such problems as fluctuation in the threshold voltage of transistors or reduction in current gain.
As one method for reducing the hot electron phenomenon, it has been attempted to weaken the electrical field in the vicinity of drain regions by attaining a smooth distribution of impurities in the drain regions. More specifically, the method may employ the so-called DDD (Double Diffused Drain) structure in which arsenic of a higher concentration and phosphorous of a lower concentration are doubly diffused in source/drain diffusion layers, or the LDD (Lightly Doped Drain) structure in which diffusion areas of a lower concentration is formed in drain regions underneath gate electrodes.
When a comparison is made between the two cases above, the DDD structure is simpler with respect to its manufacturing process. Meanwhile, by comparing them in their capability of suppressing the short channel effects which might be caused by the miniaturization, or in their electric properties such as resistivity or leakage current, it has been known that the LDD structure is superior to the other. This is described, for example, in "IEEE, IEDM 87, pp. 714-717".
Since the standard LDD structure involves, however, some problems as will be described below, an improved LDD structure has been contrived. More specifically, the standard LDD structure has n.sup.+ impurity regions of drain regions formed under sidewall oxide films of gate electrodes. Therefore, underneath the gate electrodes there is only partial encroachment of the n.sup.- impurity regions which have expanded through lateral diffusion. In such a structure, a part of the hot carriers generated in the vicinity of the drains is trapped in the sidewall oxide films. This results in the problems of increased resistivity in the n.sup.- impurity regions and decreased current gain. Meanwhile, the improved LDD structure has n.sup.- impurity regions embedded underneath gate electrodes to avoid the problems above.
Furthermore, a structure called PSD (Poly Silicon Source Drains) transistor which has applied a polysilicon layer to source/drain regions has been proposed for a submicron transistor. In the PSD transistor, the source/drain regions are formed through impurity diffusion from the overlaid polysilicon layer to the substrate. According to such a method, it is possible to make diffusion depth of the impurities in the semiconductor substrate significantly shallow to a degree of about 0.1.mu.m. Additionally, by utilizing a polysilicon layer extending over the field regions, it is possible to make a contact with source/drain regions on the field regions. This enables the reduction of the occupied plane area of a transistor, which characterizes the PSD transistor.
Now, with reference to FIG. 3, a structure of the conventional PSD transistor will be described. The PSD transistor as shown in FIG. 3 is described, for example, in "IEEE ELECTRON DEVICE LETTERS Vol 1 EDL-7 No. 5 pp. 314-316, 1986. At a surface of a silicon substrate 1 there is formed a field oxide film 2. Furthermore, at another surface of the silicon substrate 1, there are formed source/drain regions 3 and 4 at predetermined intervals in which impurities of the opposite conductivity type with respect to the silicon substrate 1 have been added. On the surfaces of the source/drain regions 3 and 4, a polysilicon layer 5 extends over the field oxide film 2. On the surface of the silicon substrate 1 lying between the source/drain regions 3 and 4, there is formed a gate electrode 7 with a gate oxide film 8 interposed therebetween. The source/drain regions 3 and 4 are of the so-called DDD structure or double diffused structure which has been formed through diffusion of the high concentration arsenic and the low concentration phosphorous both added to the polysilicon layer 5.
Meanwhile, as described above, the LDD structure should be preferably employed in a short channel transistor with respect to impurity distribution in source/drain regions, rather than the DDD structure. Moreover, it is further desirable to employ the improved LDD structure which has n.sup.- impurity regions on the drain side embedded underneath gate electrode.
As has been described in the foregoing, it is preferably required to implement an MOS transistor provided with good transistor properties and capable of accepting a miniaturized structure as a PSD transistor with the improved LDD structure.
In attempting to embody a PSD transistor of the LDD structure with the application of the well-known art, it has turned out impossible to implement the same with the aid of any existing technology due to the following various drawbacks and problems.
In the following, the features and problems of the LDD structure will be described in connection with three conventional examples.
Initially, the first example will be described with reference to FIGS. 4 and 5. The present example is described, for example, in the Japanese Patent Laying-Open No. 62-122170. FIG. 4 is a cross sectional view of a LDD MOS transistor according to the present example. The source/drain regions 3 and 4 are of the LDD structure comprising high concentration n.sup.+ impurity regions 3a and 4a and n.sup.- impurity regions 3b and 4b adjacent thereto. This LDD structure is formed as follows. Referring to FIG. 5, after a gate oxide film 8 and a gate electrode 7 are patterned to have a predetermined configuration, arsenic is implanted to surface of a silicon substrate 1 to a higher concentration through the channeling direction. In this channeling ion implantation, the implanted ions will not substantially extend in lateral directions. Subsequently, with a tilt of about 7.degree. as ion injection angle with respect to the surface of the silicon substrate 1, phosphorous is implanted to a lower concentration. In this random direction ion implantation, the ions extend laterally to about 0.05.mu.m underneath the gate electrode 7. Thereafter, a proper heat treatment is applied thereby to complete the LDD structure which has an n.sup.- impurity layer 3b, 4b of a lower concentration extending underneath the gate electrode 7.
This first conventional example is characterized by the first that the ion implantation is performed twice, i.e. first in the channeling directions and second in the random directions, and then difference in degree of the lateral extensions of the impurity ions is utilized to constitute the LDD structure. To cause channeling, it is required for the silicon substrate surface to be directly exposed. For example, if a polysilicon layer, an oxide film or the like have been formed on the silicon substrate surface, then, implanted ions are scattered while passing through the stacked layers such as the polysilicon layer in case of the ion implantation in channeling directions for the silicon substrate surface, so that channeling will not occur. This means that the channeling ion implantation can not be performed on the PSD transistor because there always exists a polysilicon layer on the surface of the silicon substrate 1. Furthermore, in the channeling ion implantation, while the lateral extension of impurity ions is negligible, the impurity ions reach to a depth more than several times that in the random ion implantation case. This makes it difficult to implement a shallower diffusion layer which is desired for a transistor of miniaturized structure. Furthermore, since the lateral extension of the low concentration diffusion layer is made by a secondary effect caused by ion scattering in the random ion implantation, the vertical and lateral extensions of the impurities cannot be determined independently of each other.
Next, the second example will be described with reference to FIGS. 6, 7A and 7B. The present example is described in Japanese Patent Laying-Open No. 62-122273. In FIG. 6, a cross sectional view of a LDD MOS transistor according to the present example is shown. Referring to FIG. 6, source/drain regions 3 and 4 are of a LDD structure comprising high concentration n.sup.+ impurity regions 3a and 4a, and low concentration n.sup.- impurity regions 3b and 4b. This LDD structure is constituted according to the processes shown in FIGS. 7A and 7B. More specifically, as shown in FIG. 7A, a second film 10 and a resist 11 both patterned to have a predetermined configuration formed on surface of a polysilicon layer 9 on a silicon substrate 1. With the resist 11 and the second film 10 as mask, impurities are ion implanted in surface of the silicon substrate 1 to form low concentration n.sup.- impurity regions 3b and 4b. After removing the resist 11, as shown in FIG. 7B, a CVD (Chemical Vapor Deposition) oxide film is deposited thereover, and anisotropic etching such as reactive ion etching is performed to form sidewalls 12 on either side of the second film 10. Furthermore, with the second film 10 having the sidewalls formed on either side as mask, the polysilicon layer 9 is etched to form a gate electrode 7. Thereafter, impurities are ion-implanted in surface of the silicon substrate 1 with the gate electrode 7 as mask to form high concentration n.sup.+ impurity regions 3a and 4a.
In this second example, the ion implantation for forming the n.sup.- impurity regions 3b and 4b is performed through the gate oxide film 8 and the polysilicon layer 9. Therefore, the ion implantation damages are induced in the gate oxide film 8. The damages cause the gate oxide film 8 to increase its trap state and reduce its dielectric strength or breakdown voltage. In order to attain a highly reliable transistor, therefore, use of the gate oxide film damaged by ion implantation should be preferably avoided.
The third example will be now described. This example is described in Japanese Patent Laying-Open No. 62-14776. FIGS. 8A and 8B are cross sectional views showing main manufacturing processes of a LDD MOS transistor according to the present example. As shown in FIG. 8A, an oxide film 13 including impurities of a high concentration is formed on a silicon substrate 1 to have a predetermined configuration through patterning. Sidewalls 14 including impurities of a low concentration are further formed on sides of the oxide film 13. Thereafter, a gate oxide film 15 is formed.
Subsequently, as shown in FIG. 8B, a gate electrode 7 of a predetermined configuration is formed. A proper heat treatment is then applied to thermally diffuse out the high concentration impurities contained in the oxide film 13 and the low concentration ones contained in the sidewalls 14 to the substrate. As a result, source/drain regions 3 and 4 of a LDD structure comprising both high concentration impurity regions 3a and 4a, and low concentration impurity regions 3b and 4b are formed.
In the present example, the thermal diffusion method is used to form impurity regions. Therefore, the extensions of the low concentration impurity regions 3b and 4b underneath the gate electrode 7 are formed through the lateral diffusion of impurities. Furthermore, there exists the disadvantage that the impurity concentrations and diffusion length in lateral and vertical directions of the source/drain regions 3 and 4 cannot be controlled independently.
As has been described above, it is difficult to attain the improved LDD structure of the PSD transistor by the existing methods.